uart Project Status
Project File:	uart.ise	Current State:	New
Module Name:	uart_rx	Errors:
Target Device:	xc3s500e-4fg320	Warnings:
Product Version:	ISE 10.1.02 - Foundation Simulator	Routing Results:
Design Goal:	Balanced	Timing Constraints:
Design Strategy:	Xilinx Default (unlocked)	Final Timing Score:

 

uart Partition Summary				[-]
No partition information was found.

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report
Translation Report
Map Report
Place and Route Report
Static Timing Report
Bitgen Report

Date Generated: 10/21/2008 - 16:35:56